At last , the layout is verified with cadence verification tools , dracula . drc ( design rule cherker ) and lvs ( layout versus schematic ) have been done successfully , which improve the feasibility of the layout design . so the whole ic design flow , from the front end to the back end of a circuit design , is completed 接著應用無錫上華標準0 . 6umcmos工藝提供的元器件模型參數進行了電路仿真,并根據尺寸設計規則設計了整體電路的的版圖,最后運用cadence中的版圖驗證工具集dracula對電路版圖成功地進行了drc ( designrulecherker ) 、 lvs ( layoutversusschematic )驗證,證明了電路版圖設計的可行性,完成了ic設計從前端到后端的設計流程。
百科解釋
The Layout Versus Schematic (LVS) is the class of electronic design automation (EDA) verification software that determines whether a particular integrated circuit layout corresponds to the original schematic or circuit diagram of the design.